Abstract
Reliability is expected to become a big concern in future deep sub-micron integrated circuits design. Soft error rate (SER) of combinational logic is considered to be a great reliability problem. Previous SER analysis and models indicated that glitch width has a great impact on electrical masking and latch window masking effects, but they failed to achieve enough insights. In this paper, an analytical glitch generation model is proposed. This model shows that after an inflexion point the collected charge has an exponential relationship with glitch duration and the model only introduces an estimation error of on average 2.5%.
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