Sn whisker evaluations in 3D microbumped structures

Abstract

Sn whiskering remains a reliability concern in electronic applications. Despite extensive research on growth rates and mitigation strategies, no predictive theory is in place. Literature data are available for Cu/Sn-based films and coatings as well as for board-level and flip-chip solder bumps but data are scarce for scaled-down solder volumes and for higher intermetallic-to-solder ratios. The current work investigates whiskers in “isolated geometries” for 3D solder-capped Cu microbumps with >2 orders of magnitude smaller solder volumes compared to state-of-the-art. To the best of the authors’ knowledge, this is the first time Sn whisker growth is reported in isolated solder volumes (e.g. <8μm-side cube). Whiskers propensity was evaluated using JEDEC industrial specifications. The tested structures were: 5/3.5μm-thick Cu/Sn films and 15μm-diameter electroplated solder capping (Sn, SnAg, SnCu) on Cu microbumps (as-plated vs. reflowed). Selected Sn whiskers and “whisker-like” features were analysed and identified experimentally with SEM, EDX and FIB. In the absence of a predictive model, first-order and “what if” calculations based on IMC molar volume and oxide cracking hypotheses were carried out. This approach quantifies “figures of merit” for Sn whisker propensity with (1) different bump-limiting metallization (BLM) cases e.g. Cu, Ni, Co and (2) further microbump scaling. Future research recommendations are outlined to mitigate manufacturing risks by controlling “sit time” between bumping and stacking.