Abstract
Networks-on-chips (NoCs) are widely used for on-chip communications in embedded multiprocessor architectures. SMART NoC achieves ultralow latency by enabling single-cycle multiple-hop transmission via bypass channels. However, the contention on the bypass channels seriously degrades the performance of SMART NoC by breaking the bypass paths. Therefore, contention-free task mapping and scheduling are essential for optimal system performance. In this letter, we propose an satisfiability modulo theories (SMTs)-based framework to find the contention-free task mapping with the minimum application schedule length. On top of the SMT’s fast reasoning capability for the conditional constraints, we develop efficient search-space reduction techniques to achieve practical scalability. Experiments demonstrate that our approach achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> higher scalability compared to integer linear programming (ILP) approach with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$599.5\times $ </tex-math></inline-formula> faster average runtime for finding an optimum solution.
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