Smart packet processor design for the cognitive packet network router

Abstract

As the Internet expands significantly in numbers of users, servers, IP addresses, and routers, the IP based network architecture must evolve and change. Recently, cognitive packet networks (CPN) was proposed as an alternative packet network architecture, where there is no routing table, instead, reinforcement learning (random neural networks) is used to route smart packets. CPN routes packets based on QoS, using measurements that are constantly collected by packets and deposited in mailboxes at routers. Previously, CPN has been implemented in a software test-bed. In this paper, we present design approaches for a CPN network processor chip. Particularly, we discuss implementation details for one of the modules in the chip: the smart packet processor, which includes a neural network hardware design.