Smart Gate Driver ICs for GaN Power Transistors

Abstract

GaN power HEMTs are known to offer high switching speed, low on-resistance and much better FOM when compared to their silicon counterparts. However, the ability to operate with high power density in a smaller form factor presents new challenges for reliable and robust operation. Traditional gate driver designs for silicon-based power devices are catered to lower frequencies with large tolerance on the gate voltage swing. They do not adequately address some of the reliability issues that are unique to GaN power transistors. This talk will provide a quick review on the gate driving requirements and limitations for GaN power HEMTs. This is followed by a survey of novel smart gate driving techniques that can further exploit the performance and enhance the reliability of GaN power devices. Topics to be covered include intelligent gate driving schemes such as active gate driving, dead time optimization, and current balancing. Emphasis will be given to designs that can be integrated and those that can monitor the devices for optimum performance and safe operation. Protection features such as short-circuit detection, gate overvoltage prevention, temperature monitoring and compensation will also be discussed. Monolithic integration of power GaN ICs is an exciting area of development with increasingly sophisticated designs reported in recent years. Fully integrated GaN building blocks and state of the art designs will be addressed.