Abstract
A small-signal analysis of the single-ended one-stage folded-cascode CMOS operational amplifier is presented. The analysis results in a four-pole two-zero representation from which a two-pole model is extracted that is sufficiently accurate for many applications in switched-capacitor (SC) circuits. A design equation for obtaining the minimum settling time (MST) response for SC applications is given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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