Abstract
This paper describes features of the Symbolic Layout System (SLS), an advanced layout system for VLSI designs. Symbolic layout is a method by which point objects, wires, and regions are sketched on a virtual grid, converted to shapes, and then spaced according to a set of minimum ground rules using a compactor. Point objects are defined as terminals, FET transistors, contacts, or vias. These objects are connected using wires or sticks. Flexible regions (orthogonal polygons) are provided for building wells, bipolar transistors, or complex devices. Network extraction is performed on the wires and point objects to check connectivity and provide net information to the compactor. The compaction process is interactively controlled, allowing the user to override design rules, insert jogs, build compaction fences, and specify the compaction center. SLS is technology independent, making it useful for bipolar and FET technologies.
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