Slot Waveguide Enhanced Field Confinement by CMOS-Compatible Hybrid Plasmonic Structures

Abstract

The surface plasmon polaritons (SPPs) have attracted considerable attention because of their ability to localize, confine, and guide electromagnetic energy at the subwavelength scale beyond the diffraction limit. Innovative waveguide structures, including slab, coaxial, dielectric-loaded and other waveguide components, have followed in the wake of the hybrid plasmonic because it features a simultaneous subwavelength mode confinement and relative long-range propagation. Here, We present an investigation of a novel slot waveguide consisting of two hybrid plasmonic strip with a metal -- Coxide -- Csemiconductor structure which can be compatible with CMOS process. Compared to a structure with homogeneous high-refractive-index silicon embedded by slot, the two plasmonic structure provides strong optical field concentration for slot waveguide. Numerical simulations based on the finite-element method demonstrated that the hybrid plasmonic slot waveguide performs relatively high optical confinement ability, that is nearly twice as much as the traditional silicon waveguide's. Furthermore, the propagation length of proposed structure can reach 46.7 um. So, the proposed structure exhibits better tradeoff between mode confinement and propagation length because of the novel structure of the layers. The proposed waveguide can be exploited for on-chip integration of Si-based electronic circuits. The optical characteristics of a new Ag -- Csilica -- Csilicon -- Csilica-slot -- Csilicon -- Csilica -- CAg waveguide can be optimized by tuning the sizes of the layers. Optimal results showed that the proposed hybrid waveguide could achieve 2D tight mode confinement with relatively low propagation loss when the height of silicon is 125nm, the height of silica is 10nm, height of Ag is 40nm with its width is 200nm. Our proposed structure can be realized using a standard CMOS fabrication process and has the potential to enable the production of compact on-chip integration.