SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling

Abstract

We present a novel systematic logic synthesis methodology, that assesses potential delay improvements in noncritical paths for any circuit. It synthesizes them with tighter constraints toward minimizing the number of near-critical paths and, as a result, reducing the probability of timing violations when frequency is overscaled. We demonstrate that our methodology reduces the number of near-critical paths by up to 93% and offer favorable accuracy and performance tradeoffs, up to $15{\times }$ reduction in error rate and $7{\times }$ reduction in mean relative error under timing speculations when compared to traditional synthesis methods. Additionally, when used together with precision scaling in cross-layer approximation techniques, it facilitates a further 27% frequency increase over an increase achievable with traditional synthesis methods. The area and power overheads of experimented circuits are up to 14% and 12%, respectively. Our methodology is compatible with traditional Electronic design automation flows. It inherits the rich feature set of existing tools and leverages their entire scope of optimizations.