Slack redistribution in pipelined circuits for enhanced soft-error rate reduction

Abstract

Soft errors are changes in logic state of a circuit/system resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Soft-error rate (SER) reduction can be achieved by using both spatial and temporal redundancy techniques. In this paper, we present a slack redistribution technique, applicable to pipelined circuits, to enhance SER reduction obtainable from time-redundancy based techniques.