Skipping algorithms for defect inspection using a dynamic control strategy in semiconductor manufacturing

Abstract

In this paper, we propose new ways for efficiently managing defect inspection queues in semiconductor manufacturing when a dynamic sampling strategy is used. The objective is to identify lots that can skip the inspection operation, i.e. lots that have limited impact on the risk level of process tools. The risk considered in this paper, called Wafer at Risk (W@R), is the number of wafers processed on a process tool between two defect inspection operations. An indicator (GSI, Global Sampling Indicator) is used to evaluate the overall W@R and another associated indicator (LSI, Lot Scheduling Indicator) is used to identify the impact on the overall risk if a lot is not measured. Based on these indicators, five new algorithms are proposed and tested with industrial instances. Results show the relevance of our approach and that evaluating sets of lots for skipping performs better than evaluating lots individually.