Abstract

This work shows the usefulness of assigning current-branches-bias levels, in order to improve and accelerate the sizing optimization of MOSFET-based analog integrated circuits (ICs). That way, the proposed procedure relies on the search of current branches from the associated incidence matrix by applying a recursive technique for exploring circuit graphs. The goal is focused on determining the bounds of the width/length (W/L) search space for each MOSFET before starting the sizing optimization process. As a case of study, the proposed current-branches-bias assignment (CBBA) approach is applied in the sizing optimization of the recycled folded cascode operational transconductance amplifier by applying evolutionary algorithms (EAs). From the feasible optimization results, we conclude that our proposed CBBA approach enhances and accelerates the biasing and sizing of analog ICs by EAs. DOI: http://dx.doi.org/10.5755/j01.eee.19.10.2464

Highlights

  • The sizing optimization of analog integrated circuits (ICs) by applying heuristic approaches has grown in the last decade [1]–[8]

  • The last section discusses the results provided by the three evolutionary algorithms (EAs) with both genetic operators and with and without applying our proposed current-branches-bias assignment (CBBA) approach

  • A current-branches-bias assignment (CBBA) approach has been introduced in order to improve and accelerate the sizing optimization process of analog integrated circuits (ICs) composed of MOSFETs

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Summary

INTRODUCTION

The sizing optimization of analog integrated circuits (ICs) by applying heuristic approaches has grown in the last decade [1]–[8]. The usefulness of our proposed CBBA approach is demonstrated by sizing the recycled folded cascode (RFC) operational transconductance amplifier (OTA) given in [9], by applying three EAs, namely: non-dominated sorting genetic algorithm (NSGA-II) [13], multi-objective EA with decomposition (MOEA/D) [14], and multi-objective particle swarm optimization (MOPSO) [15]. These EAs have been applied to sizing analog ICs in [1], [2], [4], [6]. Those results demonstrate that CBBA improves and accelerates the sizing optimization process of analog integrated circuits

TOPOLOGICAL CIRCUIT ANALYSIS
APPLICATION EXAMPLE
Findings
OF RESULTS
CONCLUSIONS
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