Size-free MEMS-IC high-efficient integration by using carrier wafer with self-assembled monolayer (SAM) fine pattern

Abstract

Wafer level integration of MEMS with IC will dramatically improve integration efficiency and reduce production cost. However, up to date, the large residual stress and the none-flat surface of MEMS processed wafers are still intractable problems. Besides, the expensive through-silicon vias (TSVs) process and the limitation of both die size and wafer size in wafer level integration are other difficult barriers that strictly restrict the flexibility of MEMS structure design and fabrication process. Therefore, a flexible approach by using self-assembled monolayer (SAM) coated carrier wafer was developed in our work for size-free MEMS and IC integration. First, MEMS and/or IC dies are self-aligned and temporarily bonded onto binding-sites, which was defined by hydrophobic-SAM (FDTS, CF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (CF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sub> (CH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SiCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) on carrier wafer. Then, those dies are simultaneously transferred to target IC processed wafer or interposer wafer by wafer level permanent bonding. The vapor phase deposited and lift-off patterned hydrophobic-SAM, FDTS, allows high speed self-align of MEMS and IC dies with various sizes and thicknesses onto binding-sites by surface tension of H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O with high accuracy (<;1μm). Carefully designed FDTS fine pattern was also proved effective to control the bonding strength (die shear strength <;0.01 kgf with controlling by FDTS; 3.5~4.0 kgf without FDTS fine pattern). It enables easy debonding of those dies from carrier wafer after permanent bonding step. An experimental prototype system was developed to investigate the process parameters, e.g. volume of H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O for self-assembly, wafer temperature for H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O evaporation, annealing process for bonding strength control, and etc. This simple and low cost approach offers unique merits of high flexibility in both geometries of the dies/wafers and processes of the devices with reasonably high efficiency when compared to C2C or C2W integration. This approach will be considerably valued for prototype development and low-medium volume production of MEMS-IC integrated systems, e.g. wireless sensor nodes.