SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships

Abstract

We present SI-SMART, a hybrid Swarm Intelligence and Satisfiability Modulo theory based Automatic Register Transfer level test generator. Traditional Bounded Model Checking (BMC) or symbolic execution based methods depend upon multi-cycle circuit unrolling/analysis for stimuli generation. The presence of loops in the design under test (DUT) typically limits such methods, resulting in lower design coverage. SI-SMART tackles this problem by eliminating explicit unrolling of the control flow graph (CFG). This is achieved by abstracting loops present in the design under test (DUT) and attempting to learn the recurrence relations among the variables that directly or indirectly affect the target branch condition. An SMT solver is used to find correlations between the inputs and the target branches. This learned knowledge is later fed back to a combination of Binary Particle Swarm Optimization (BPSO) and Hooke Jeeves method to attempt to reach the uncovered branches. SI-SMART is evaluated on several difficult variants of ITC99 benchmark circuits. 100% branch coverage is achieved in almost all circuits with significant improvement in branch coverage, test sequence lengths and execution times over existing methods.