Single-Phase Enhanced Phase-Locked Loops Based on Multiple Delayed Signal Cancellation Filters for Micro-Grid Applications

Abstract

The grid voltage information such as the phase-angle, the frequency, and the amplitude is crucial for the design of synchronization and control of power converters in the micro-grid. The conventional approach to estimate the grid voltage information is accomplished by phase-locked loop (PLL) techniques. Among various existing PLL techniques, filter-based PLLs can provide more accurate estimations even under adverse grid conditions. In this paper, a new single-phase filtering technique based on multiple delayed signal cancellation (MDSC) is proposed for extracting both in-phase and quadrature components of the selected harmonic order of the single-phase grid voltage signal. This MDSC technique can be realized in both the direct-form and the recursive-form. In comparison with existing single-phase cascaded delayed signal cancellation (CDSC) techniques, this MDSC technique utilizes less memory for the extraction of grid voltage fundamental frequency component. The proposed MDSC filter can be applied as a pre-filter to the enhanced PLL (EPLL) for the prompt and accurate estimations of the grid voltage information under adverse grid conditions. Both frequency adaptive and non-adaptive MDSC-based EPLL schemes are proposed in this paper. To validate the effectiveness of the proposed methods, experiments are conducted on the MDSC-based EPLLs and compared with the CDSC-EPLL under various grid voltage disturbances.