Abstract
In this paper, single-event upset (SEU) is predicted using a combination of technology computer aided design (TCAD) and Geant4 Monte Carlo simulations. According to the layout topology of a 65 nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) arrays, the sensitive volumes (SVs) of off and on-transistors were calibrated by TCAD using novel circuit schematics. The effects of on-transistor charge collection on SEU were studied, and a novel criterion for SEU occurrence is proposed. Heavy ion simulation results indicate that the probability of SEU recovery increased with increased ion energy and striking tilt. The simulated SEU cross section and multiple cell upsets (MCUs) percentage based on the proposed method are in agreement with the experimental data for 6 T SRAM cells, which were fabricated using 65 nm processing technology.
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