Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors

Abstract

RF power transistors are typically operated at extreme drain voltage and current peaks, which cause severe impact ionization conditions at the channel pinch-off region. On a SOI CMOS technology platform, the resulting large body currents may eventually lead to single transistor latch-up, unless the length of the gate/body finger is properly chosen. In this work, the effect of single-transistor latch-up on the large-signal performance of SOI CMOS RF power transistors is investigated for the first time. Extensive multi-harmonic load–pull measurements have been performed to characterize the resulting current runaway phenomenon and its detrimental effect on the device efficiency. Useful guidelines have been derived to avoid such limitations and a prototype power transistor has been designed accordingly. Thanks to the proposed design criteria, the device achieves latch-up-free operation at the nominal 2-V supply voltage, while exhibiting an excellent 72% power-added efficiency at a 19.5-dBm output power level under 1.9-GHz continuous-wave excitation. Moreover, an experimental study on the gate oxide degradation kinetics under RF stress has been carried out to characterize the long-term device reliability of the adopted SOI CMOS process.