Single Pulse Unclamped-Inductive-Switching Induced Failure and Analysis for 650 V p-GaN HEMT

Abstract

This letter firstly reveals the single pulse unclamped-inductive-switching (UIS) withstanding physics and failure mechanism for p-GaN high electron mobility transistor (HEMT) with Schottky type gate contact. Unlike silicon/silicon carbide (Si/SiC)-based devices, the p-GaN HEMT withstands the surge current from load inductor by storing the energy into the output capacitance of the device, rather than dissipating the energy by avalanche process. To describe the UIS process, physics-based models are proposed. Also, by the simulations and de-cap/de-layer experiments, the failure mechanism is presented as a different manner compared with Si/SiC-based devices. The high voltage during the UIS process introduces high electric field near the drain contact, which leads to the inverse-piezoelectric effect, then bringing the rise-up of the leakage current and high power dissipation. As a result, the region near drain contact is burned by thermal runaway. Moreover, it is demonstrated that higher bus voltage and larger load inductance will increase the UIS-induced failure risk, while the gate resistance, turn- off gate voltage and ambient temperature exhibit little influences upon the UIS withstanding capability of the device.