Abstract
A novel topology for active power filters (APF) has been proposed. This filter can be used in combination with passive parallel filters effectively to reduce the power rating of the active filter. Hence, if no power-factor compensation at fundamental frequency is required, then during steady state only a small fraction of harmonic current flows through this filter which effectively reduces the size and power dissipation of the filter. A major issue in control of parallel and series active power filters is their tendency to oscillate in the presence of certain kinds of reactive load. This problem becomes even worse when control loops with one-cycle control delay using digital signal processors are implemented. The proposed topology is relatively immune from such load–source-impedance-interaction. This filter can provide a cost-effective solution for system-integrated design where the filter is supposed to be the part of the application. The proposed system has been studied analytically and tested using computer simulations and experiments.
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