Abstract
Low Density Parity Check codes (LDPC) have shown good error correcting performance which enables efficient and reliable communication. A subclass of LDPC codes known as quasi-cyclic LDPC codes are used whose parity check matrices consists of circulant permutation matrices. QC-LDPC codes require less memory as compared to LDPC codes. This paper presents a low complexity quasi-cyclic low density parity check (QC-LDPC) decoder. QC-LDPC codes require less memory as compared to LDPC codes. Partially parallel, low complexity decoder architecture has been designed for single-mode decoding. This decoder is modeled in Verilog, synthesized and performed place and route for the design using Xilinx ISE 12.1.
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