Abstract
Large-scale telecommunication systems in the larger nationwide network of the next decade will require routers having a packet switching throughput capacity of over several-tens Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. In this paper, we describe an SFQ packet switch architecture that is used in the internal speed-up Banyan network. According to the architecture we have designed and demonstrated a deep-pipelined 2/spl times/2 packet switch logic circuit, which is the key element in a packet switch, by applying two technological advances regarding design methodology and packaging. This circuit is among the largest SFQ random logic circuits yet reported.
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