Single event transient tolerant frequency divider

Abstract

This study presents a single event upset (SEU) tolerant frequency divider that compares the counted number of rising clock edges with the expected value. The number of counted rising edges being less than expected generally implies that the state is corrupted resulting in faulty output, so the faulty frequency divider is reset to a proper state to correct errors. The number of counted rising edges being greater than expected generally implies that the output is corrupted by a single event transient (SET) without changing the state, hence SET tolerance does not require a reset. Simulation and experimental results demonstrate that the proposed scheme can achieve high operational clock frequency and good SEU hardening capability.