Single-Event-Hardened All-Digital Delay Generator for FPGA-Based Implementation of a TDC-based readout electronics

Abstract

This paper addresses the single-events effects on an all-digital delay generator and also investigates the propagation and impact of soft errors in the all-digital delay generator caused by the single-event transients to the time-to-digital converters. The all-digital delay generator is implemented using an array of all-digital delay-locked loops with error correction circuit for improved single-event transients resilience and uses the time interpolation technique for achieving 5 ps sub-gate delay resolution. The effectiveness of the mitigation of single-event upsets and the robustness of the architecture is demonstrated through the simulations in 90 nm CMOS technology at linear energy transfer up to 100 MeV⋅cm2/mg. The portability of the mitigation technique is validated by the results obtained through an FPGA implementation of the all-digital delay generator.