Single-chip 4×500-MBd CMOS transceiver

Abstract

This CMOS chip replaces a 72-wire interface with 4 serial, duplex links, for relief of interconnect congestion in applications such as large switching systems. The design supports transmission at 1.6 Gb/s per direction in full-duplex mode and provides the user with a transparent interface. The data source provides fixed-length synchronous packets segmented into 4 parallel bytes along with parity and flag bits. The packet size can be programmed up to 4/spl times/64 B with a parameter loaded from an external controller. Data packets can he transmitted contiguously. During idle periods that are marked by a flag, the circuit generates and transmits fill packets, which start with a non-data Comma character. The Comma marks both byte and packet boundaries on a serial link. The Fill packets carry an idle sequence or diagnostic and control information such as Not Operational, Remote Wrap, or Unwrap. Each link carries 400 Mb/s, corresponding to 500 Mbaud after 8 B/10 B encoding.