Single Bit Fault Detecting ALU Design using Reversible Gates

Abstract

The semiconductor industry has been experiencing a massive upgradation in terms of speed and device performance due to device scaling since the invention of MOSFETs in 1960s, but simultaneously power dissipation has also been a major concern. With the device scaling having reached its limit, researchers are looking for a breakthrough technology. One of the emerging fields in the VLSI industry is Reversible Computing. This technology has largely attracted the researchers, because of zero power dissipation in reversible logic circuits. The proposed work here is towards designing an ALU using reversible quantum gates, which operate on qubits. The proposed ALU performs both arithmetic and logical operations, either of which can be selected as per the requirement and additionally, it is capable of detecting single bit error. The design uses Fredkin and CNOT gate, which are parity preserving reversible gates. The proposed design is modelled using Verilog HDL and simulated in Modelsim software. The design is focused on reducing the number of gates, quantum cost, Garbage outputs and ancillary inputs or constant inputs.