Simultaneous power and thermal integrity driven via stapling in 3D ICs

Abstract

The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steady-state thermal analysis. This paper presents the first in-depth study on simultaneous power and thermal integrity driven via-stapling in 3D design. The transient temperature and supply voltage violations are calculated by a structured and parameterized model reduction, which also generates parameterized temperature and voltage violation sensitivities with respect to the via pattern and density. Using parameterized sensitivities, an efficient yet effective greedy optimization is presented to optimize power and thermal integrity simultaneously. Experiments with two active device layers show that compared to sequential power and thermal optimization using steady-state thermal analysis, sequential optimization using transient thermal analysis reduces non-signal vias by on average 11.5%, and simultaneous optimization using transient thermal analysis reduces non-signal vias by on average 34%. The via reduction would be higher for the 3D design with more device layers