Simultaneous Optimization of the Material Properties, Uniformity and Deposition Rate of Polycrystalline CVD and PECVD Silicon-Germanium Layers for MEMS Applications

Abstract

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work an optimized process to deposit high quality crystalline poly-SiGe layers with low stress, low strain gradient and good within-wafer uniformity at a manufacturable throughput is developed. The process used to deposit the layers is based on a combination of CVD and PECVD SiGe depositions. Firstly, the CVD SiGe process has been extensively characterized to the extent that the influence of thickness, Ge concentration and B concentration on film stress and strain gradient is now well understood. Then the interaction between the PECVD SiGe and the underlying CVD layer has been investigated. This combined knowledge enables specific tailoring of the CVD-PECVD SiGe stack to give the desired strain gradient for a certain layer thickness.