Simultaneous improvement of area, delay, and fault tolerance in quantum circuits

Abstract

Fault tolerance is a necessity for successful realization of quantum circuits. Achieving fault tolerance in quantum circuits is more complicated than classic circuits due to their inherent characteristics such as error continuum, destruction of quantum state after measurement, and no-cloning. Adding fault tolerance should incur a reasonably minimal overhead in latency and area. In this paper, a new approach for implementation of fault tolerant quantum circuits is proposed. The correction blocks are arranged in such a way that the overall circuit area and delay are reduced. This will also lead to a reduction in error distance in the circuit. The correctness of the proposed approach is mathematically proven in the paper. Experimental results confirm the analytical expectations and show an average improvement of 47.8% in terms of delay, 17.6% in terms of area, and 47.8% in terms of error distance.