Simultaneous DC Current Balance and CMV Reduction for Parallel CSC System With Interleaved Carrier-Based SPWM

Abstract

Parallel current source converter (CSC) has attracted increasing attention due to the potential advantages to increase the system power capacity, reliability, and output quality. Compared with multilevel space vector modulation (SVM) and selective harmonic elimination, carrier-based sinusoidal pulsewidth modulation (SPWM) enjoys inherent scalability and modularity, which is very easy to be implemented in N-CSC parallel system by interleaving the carriers. The dc current balance and common-mode voltage (CMV) are the main concerns in parallel CSC system and most of the research was focused on SVM. However, dc current balance and CMV reduction methods with interleaved SPWM were not well addressed. In this article, we mainly investigate three different interleaved SPWM methods, namely, bi-tri logic SPWM, six-step direct PWM, and direct duty-ratio PWM (DDPWM). The comparison results show that the proposed interleaved DDPWM can balance the dc current and suppress CMV simultaneously, which can improve the output quality and reduce load-side CMV stress effectively. The validity and effectiveness of the proposed methods are verified on a parallel CSC system with shared dc-link by simulation and experimental results.