Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign

Abstract

With the increasing complexity of circuit design in recent years, the pin assignment and escape routing problems for FPGA on a PCB have become greatly difficult due to the fast increase in pin count and density. Most existing works only focus on either the FPGA pin assignment problem or the PCB escape routing problem independently but cannot handle them simultaneously. In this paper, we propose an integer linear programming (ILP) based method to simultaneously solve the pin assignment and escape routing problems for FPGA-PCB code sign. Because of the underlying network structure of our formulation, we can solve the problem efficiently. Experimental results demonstrate that our method can achieve an average 54.5% wire length improvement over the common two-stage approach.