Simultaneous clock scheduling and buffered clock tree synthesis

Abstract

This paper considers the problem of designing the topology of a clock distribution network in a synchronous digital system so as to enforce nonzero clock skew. A methodology and related algorithm for synthesizing the topology of the clock distribution network from a clock skew schedule derived from the circuit timing information is presented. The application of the algorithm to benchmark circuits shows that improvements of the minimum clock period ranging up to 64% can be achieved. These improvements are attained by exploiting non-zero clock skew throughout the synchronous system. Mathematically the problem of designing the clock distribution network is formulated as an integer linear programming problem which is efficiently solvable. The algorithm for synthesizing a clock tree is demonstrated on an example circuit.