Abstract

Silicon quantum dots (QDs) are essential physical carriers of quantum bits (qubits) in quantum computing. However, their extremely small size renders them highly sensitive to both the fabrication process and surrounding environment. Accuracy and stability must be carefully considered. In this study, we propose a double gate QD device model based on silicon metal-oxide-semiconductor (Si-MOS) for the generation of spin qubits. Using a Technology Computer Aided Design (TCAD) simulation, we investigated the impact of device dimensions, including oxide layer thickness, channel length, and spacer length, on the QD structure. Additionally, we examined the effects of the temperature and interface trap concentration on QD formation. An equivalent circuit model was employed to assess the charging energy (Ec) of QDs. Our results demonstrate that by appropriately adjusting these parameters, it is possible to achieve a QD structure with a wide level spacing and small size capable of accommodating as few as four electrons. Furthermore, we calculated an Ec of 33 meV for the QDs.

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