Simulation Study of the Instability Induced by the Variation of Grain Boundary Width and Trap Density in Gate-All-Around Polysilicon Transistor

Po-Jui Lin,Yung-Yueh Chiu,Frederick Chen,Riichiro Shirota

doi:10.1109/ted.2021.3059185

Abstract

A macaroni type gate-all-around polysilicon transistor with a single grain boundary (GB) is precisely simulated to elucidate the impacts of the variation of GB width ( W GB ) and trap density ( D t ) on its transfer characteristics. At the weak inversion region, the shift of the threshold voltage and subthreshold swing caused by GB are almost determined by the total number of the trap state in the GB ( ∝ W GB ×D t ) because the potential barrier is simply the function of total trap state number. On the other hand, the drain current in the strong inversion region ( I D,INV ) is not simply the function of W GB ×D t , but more sensitive to the variation of D t than that of W GB . For example, I D, INV becomes half when D t increases five times (from 0.2×10 21 to 2×10 21 cm -3 ·eV -1 ) with W GB ×D t kept constant ( W GB reduces from 5 to 1 nm). At the strong inversion region, the higher D t makes the deeper potential barrier at the center of GB, which reduces I D, INV further. Accordingly, the activation energy of I D, INV also has stronger dependence on D t as compared to W GB . Finally, it is shown that abovementioned characteristics are available even in the multiple-GB cases when the grain size is twice larger than the GB width.

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