Simulation study of a novel thin layer SOI carrier-stored TLIGBT with self-biased pMOS

Abstract

A novel thin layer Silicon-On-Insulator (SOI) carrier-stored (CS) trench lateral insulated gate bipolar transistor (TLIGBT) with P-shield layer and self-biased pMOS is proposed. The potential of the P-shield layer is clamped by the self-biased pMOS, which transfers the reverse voltage-sustaining position from the P-base/carrier-stored layer (CSL) junction to the P-shield/N-drift junction during the off-state. Therefore, the doping concentration of the CSL (NCS) can be increased by several orders of magnitude to decrease the on-state voltage drop (Von) without jeopardizing the breakdown voltage. Moreover, the self-biased pMOS shunts most of the hole current during on-state when the voltage of the collector is further increased, which clamps the drain-to-source voltage of the intrinsic nMOS. Then, low saturation current and large forward biased safe operating area are obtained for the proposed TLIGBT. The simulation results reveals that the turn-off loss (Eoff) of the proposed TLIGBT at Von ≈ 1.35 V is reduced by 25.4% and 41.9% compared with those of the conventional TLIGBT A and conventional TLIGBT B, respectively. Besides, the saturation current density of the proposed TLIGBT is reduced by over 44% compared with those of the conventional ones. Consequently, the short-circuit withstand time is improved by over 164%.