Simulation of the bias stress-induced hump, observed in the transfer characteristic of Amorphous Oxide Thin-Film Transistors

Abstract

The deformation in the subthreshold region of the transfer characteristic observed in Amorphous Oxide Semiconductor (AOS) Thin-Film Transistors (TFTs) is simulated, analyzing its origin. We show that, when the density of positively charged states at the back interface between the active and the passivation layer becomes sufficiently high, a parallel current path is formed between drain and source at the back of the structure. This leakage current gives rise to a deformation or hump in the transfer curve. During DC bias stress, the density of charged back interface states can increase due to carrier trapping or trap creation, depending on the intensity and time duration of the applied gate bias, as well as on the materials of the passivation layer and fabrication conditions of the devices. This explanation is in agreement with experimental data for AOS TFTs.