Simulation of Substrate Coupling with Special Regard to Shielding in High-Speed Si/SiGe Bipolar ICs

Abstract

Due to the increasing operating speed, the parasitic influence of the substrate in advanced Si and SiGe bipolar ICs tends to become more and more important and must be accurately taken into account already during circuit design. Moreover, the parasitic substrate coupling calls for shielding measures whose effectiveness at very high frequencies must be carefully checked as well. Therefore, in this paper a procedure for substrate modeling is described that has already been applied successfully in practice. For this, the numerical simulator SUSI has been developed and used to calculate the behavior of the substrate from the layout and from technological data. It has been verified by on-wafer measurements up to 40 GHz, as will be shown here for long-and short-distance substrate coupling with and without shielding. As an important application of SUSI, the reduction of substrate coupling by guard rings or by a, channel stopper layer is demonstrated. It is shown that shielding measures, however, can lose their effectiveness at very high frequencies due to the parasitic inductance of their metalization. Moreover, the results of the numerical simulation can be used to derive equivalent circuits which are necessary to model the influence of the substrate in circuit simulation.