Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL

Abstract

Improving the performance of on-chip caches has been continually regarded with much effort to provide solution to the increased performance gap between microprocessor and memory. Proposed new design techniques were mostly implemented in software simply because it is easier and faster than hardware implementation. However, with the microprocessor technology advancement, this approach fails to consider other crucial matters such as power and area. To investigate and further evaluate the dynamic partitioning schemes in a shared L2 cache in Chip Multiprocessors (CMP), we have come up with a model to bring together generated traces from the M5 simulator and the hardware implementation of a shared L2 cache described using Verilog Hardware Description Language (HDL) and developed using the Synopsys EDA tools. The use of this system model offers a number of benefits such as the following: (1) L2 cache designs can now be characterized using power and area measurements and not just performance gain alone, (2) processor and L1 caches can be abstracted away from the design to provide more focus, (3) standard benchmark can still be used to evaluate the different designs being compared, and (4) a more realistic design that is closer to getting materialized can be produced.