Abstract
Vertical MOSFET has been introduced in the last few decades. As planar devices become smaller and smaller, vertical MOS transistor is one of the solutions for surpassing the short channel effects and pattern transfer. Thus, it is a promising approach to achieve channel lengths between 100 nm and 25 nm. In this work, we simulate sub‐100 nm single channel length vertical silicon MOSFET. The simulations are done with using ATHENA, DEVEDIT and ATLAS from SILVACO International. Input and output electrical characteristics of the vertical MOS transistors are investigated. The short channel effects of the vertical MOSFETs are explored. Due to the structure is not symmetry, source at top and bottom is also considered. The results also compared with experimental results from other researcher.
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