Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator

Abstract

The static power consumption of networks-on-chip (NoCs) has been increasing across each technology generation. Power-gating is a very promising approach that can dramatically reduce NoC static power but may potentially cause substantial performance penalty. Significant research is needed to explore effective ways of applying power-gating to NoC routers. To enable further research advancement, cycle-accurate NoC power-gating simulation infrastructure is much needed. In this work, we identify key requirements for NoC power-gating simulation and discuss three important optimizations that can enable such simulators to handle router pipeline draining and handshaking correctly and efficiently. We also propose Agate, an effective NoC power-gating simulator that satisfies the key requirements and optimizations. It can be integrated into Gem5 for closed-loop, full-system simulation of NoC-based many-core computing systems. We demonstrate the capability of Agate by simulating and evaluating several power-gating schemes, including the recently proposed Power Punch power-gating scheme.