Simulation of JLFETS Using Sentaurus TCAD

Abstract

Technology computer aided design (TCAD) tools facilitate the analysis of the microscopic properties of the field‐effect transistors (FETs). This chapter introduces the basics of how the Sentaurus TCAD works and explores the simulation of junctionless field‐effect transistors (JLFETs) in Sentaurus. It discusses the basic tool flow of the most commonly used TCAD Sentaurus and provides a detailed analysis of a demo command file for both creating structure and running the device simulations for long‐channel JLFETs. The procedure for model calibration of short‐channel JLFETs and nanowire FETs (NWFETs) are also introduced. The chapter presents an insight into the simulation and calibration methodology for 3D architectures such as the gate‐all‐around NWFETs (GAA NWFETs). The calibrated simulation decks provided for the NWFETs and JLFETs in the chapter enable the new researchers in this area to explore these devices in detail and to propose new architectures to mitigate the challenges for these FETs.