Simulation of implant free III-V MOSFETs for high performance low power Nano-CMOS applications

Abstract

The potential of implant free III-V MOSFETs for high performance, low power nano-CMOS applications is studied using Monte Carlo (MC) device simulations. The viability of this III-V MOSFET architecture is first demonstrated by presenting experimental results from implant free III-V MOSFETs fabricated at Glasgow. The measured 1 μm gate length implant free transistors feature high- κ gate dielectric, metal gate and low resistance ohmic contacts. They have a positive threshold voltage V T = 0.1 V and deliver a drive current I on , = 325 μA/ μm at V G = V D = 2 V. The Glasgow finite element heterostructure Monte Carlo device simulator has been carefully calibrated against HEMTs with low and high In content in the channel fabricated at Glasgow and transport data measured on implant free layer structures with high- κ gate dielectric grown at Glasgow and Freescale. The performance of implant free III-V MOSFETs with low In content in the channel is simulated and compared for aggressively scaled devices with channel lengths below 30 nm.