Simulation of gate lag and current collapse in gallium nitride field-effect transistors

Abstract

Results of two-dimensional numerical simulations of gate lag and current collapse in GaN heterostructure field-effect transistors are presented. Simulation results clearly show that current collapse takes place only if an enhanced trapping occurs under the gate edges. Hot electrons play an instrumental role in the collapse mechanism. The simulation results also link the current collapse with electrons spreading into the buffer layer and confirm that a better electron localization (as in a double heterostructure field-effect transistor) can dramatically reduce current collapse.