Simulation of Convolutional Encoder and Viterbi Decoder using Verilog

Abstract

In this paper, we are implementing the Convolutional encoder and viterbi decoder with code rate 2/3 using verilog. The main issue of this paper is to implement the RTL level model of Convolutional encoder and viterbi decoder, with the testing results of behavior model. We tried to achieve a low silicon cost. The viterbi algorithm, used for Convolutional codes extensively employed decoding algorithm for Convolutional codes. This paper is realized using verilog HDL. It is simulated and synthesized using Modelsim Altera 10.1d. General Terms Convolutional codes were first introduced by Elias in 1955 as an alternative to block codes. Convolutional codes differ from block codes in that the encoder contains memory and the n encoder outputs at any time unit depend not only on the k inputs but also on m previous input block. In 1963, Massey proposed a less efficient but simpler to implement decoding method called threshold decoding. Then in 1967, Viterbi proposed a maximum likelihood decoding scheme that was easy to implement for codes. This scheme is called viterbi decoding.