Simulation-Based Power Estimation for Low-Power Designs: A Fractal Approach

Abstract

Low-power CMOS integrated circuit design requires accurate power estimation at every level in the hierar chy. In this paper, the Fractal Compaction Algorithm is presented. It is based on fractal concepts and is used to generate a compacted vector that allows fast, accurate simulation-based power estimation. Typi cally, power estimation methods are either dynamic or static. Dynamic methods simulate the design using specific input vector sets and estimate power. Though accurate, these methods require long simulation time for larger designs. Static power estimation methods, on the other hand, are based on analytical tools that estimate power quickly but with less accuracy. To achieve the accuracy of dynamic methods and the speed of static methods, one approach is to generate a com pact, representative vector set with switching behav ior similar to the original set. The algorithm gener ates a compact vector set by exploiting the correlation in the toggle distribution of the circuit's internal nodes. Experiments on ISCAS85 benchmark circuits with a vector set size of 4000 results in a compaction of 65.57X (max) and 38.14X (avg) with power estimation error of 2.40% (max) and 2.06% (avg). The reduction in simu lation time translates into a shorter design phase and quicker tape out. Compaction results for various vec tor sizes are also presented.