Simulation Based Analysis of I-V Characteristics of ZnO Thin Film Transistor at Channel Length 40nm

Abstract

For future low-priced electronics, high performance thin film transistors (TFTs) are highly desirable. One possible way towards device optimization is the downscaling of the channel length (L) which allows higher device density, smaller device configuration and better performance. In this paper, we present a simulation study of bottom gate TFTs based on ZnO as semiconductor, SiO2 as insulator layer and aluminum metal as drain/source contacts with channel lengths L from 50nm down to 30nm. The analysis is done using the two characteristic curves that is current/gate-voltage (ID-VG) curve and output characteristic (ID-VD) curve. The different parameters such as threshold voltage, on off current ratio and drive current are studied for different process parameters like gate oxide thickness, channel doping and channel width. To analyze that if the variation in parameters with downscaling is achievable, the simulated results are verified with theoretical results using mat lab.