Simulation and performance evaluation for network on chip design using OPNET

Abstract

Network on chip (NoC) is an emerging paradigm that copes with the increasing complexity and communication requirements of future system on chip (SoC). To further enhance performance, the design parameters of the NoC should be chosen based on the application. In this paper, we use network simulator OPNET for modeling and simulating NoC at high level chip design. We investigate various configurations of NoC architectures by varying the network topologies (2D mesh, Fat-Tree and Butterfly Fat-Tree) and switching techniques (wormhole and virtual-cut-through) and simulate each of these under different injection rates and traffic patterns. Detailed comparative analysis of the simulation results in terms of latency and throughput are presented. The results can be used as a guideline for NoC designers to make appropriate choices in order to achieve optimal performance.