Simulation and performance analysis of 15 NmFinFETbased carry skip adder

Abstract

AbstractVarious changes in the advanced semiconductor industry, designing adder with higher performance is a major concern. These proposed works constrain the major area in FinFET designing at the range of 15‐nm FinFET technology at 25°C. By designing the FinFET technology with the range of 15 nm is the rising transistor technology with the lesser delay and the management in the power tradeoff. FinFET technology makes the evolutionary step in the semiconductor field because various adders have various complications in scaling at the range of 15 nm. The speed reinforcement is used based on various schemes to improve the efficiency of the conventional carry skip adder (Conv‐CSKA) structure. By taking into account multiplexer logic, the proposed designing structure made in the account of AND‐OR‐Invert (AOI) and OR‐AND‐Invert (OAI) compound gates which are used as the skip logic. The simulation is carried out using HSPICE and Tanner. In various research works, it is concluded that the FinFET based adders are implemented in the semiconductor devices which are the advanced part of the computerized technique with the advancement in the designing circuits. The proposed designing structure includes the 8 T adders which reduce the power consumption with different datapath. The modified designing increases the slack time and decreases the input voltage. This article implements the comparison of FinFET designing based on their speed, power, and energy with the other adder circuits using 15‐nm FinFET technology.