Abstract
It is well known that thermal stress not only effects the reliability and life time of the packaging but also the device characteristics, which is crucial in microwave and millimeter wave design. A three dimensional finite element (3DFE) thermal stress simulator, scanning probe microscopy (SPM) measurements and nanometer surface profiler (DEKTAK) accompanied with a Peltier element (PE) have been used to determine the thermal stress distribution in the standard structure of QMIT. In this method by measuring and mapping the surface profile of Si-wafer around the embedded devices using SPM and DEKTAK the induced thermal stress is determined. Effects of different parameters such as baking temperature, power dissipation of the embedded GaAs-FET, geometry and elastic properties of thermal conductive epoxy have been described in detail. In all simulations a new model of QMIT with a minimum-number of nodes has been introduced. Remarkable agreement between calculated and measured displacements created by thermal stress was found.
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