Simulation and experimental study of 3-step junction termination extension for high-voltage 4H-SiC gate turn-off thyristors

Abstract

The 4H-SiC NPN structure with a 3-step junction termination extension (JTE), which shows a great capability for control of both the peak surface and bulk electric fields at breakdown, has been investigated and optimized using Synopsys Sentaurus, a two-dimensional (2-D) device simulator. The experimental results show that the NPN structure with an optimized 3-step JTE can accomplish a high breakdown voltage of 7630V, reaching more than 90% of the ideal parallel plane junction breakdown voltage. A good agreement between simulation and experimental results can be observed. The key step in achieving a high breakdown voltage is controlled etching of the epitaxially grown n-doped layer to reach the optimum depth and balanced charge in the multistep junction termination extension (MJTE) layer.