Simulation and Experiment of Molded Underfill Voids

Abstract

The molded underfill (MUF) has become one of the trends in the IC packaging industry due to its simplification of assembly process steps and the saving of the cost. However, for the fine pitch flip chip bumping array, the void generation is one serious issue causing the short of the electrical connections and the cracking of the bumps. In this paper, the main focus is to predict the void generation and to compare with the experimental data. The early stage FEM numerical simulation not only can predict the risk of voids but also provide the best economic approach without the need to spend trial and error budget. A multiple segments substrate strip, with totally 64 packages populated on it, is used in the experiment. The manufacturing process parameters are programmed and recorded for comparison. The filling, packing, and curing of molding compound are carefully chosen in order to compare their effects. After the assembly process, each package is scanned with C-SAM inspection to check if the voids appear. For FEM numerical simulation, only one segment of the substrate strip, with totally 16 packages, is modeled to save computational resources and time. However, all the bumps, on each of the package, are modeled in order to check how the flow field is affected by the packages. In conclusion, we have obtained good match of experimental vs. simulation data. The prediction of voiding location is very close to each other.